ISSN : 2319-7323

INTERNATIONAL JOURNAL OF COMPUTER SCIENCE ENGINEERING

ABSTRACT

Title	:	Design and Analysis of 8T/10T SRAM cell using Charge Recycling Logic
Authors	:	Rukkumani V, Devarajan N
Keywords	:	SRAM cell ;8T/10T memory cell;CR logic;CMOS Technology
Issue Date	:	July 2015
Abstract	:	Normally charge recycling (CR) logic is used to reduce power in SRAM memory cells.The read access time of 8T SRAM cell is slightly degraded in read �0�� operation. When the cell is in zero state, the bitline discharge along BT takes longer due to lower conductance of NMOS transistor.Two 4X4 SRAM macros have been implemented in a standard 180 nm CMOS process using the 8T and the 10T cells. Both macros have identical address decoders, data-line drivers and sense amplifier design. Extensive Read/Write operations have been simulated at 25,50,75 and 100� C to evaluate the performance of the proposed design. All the circuits simulations are designed with 250 MHz and 300 MHz operating frequency with supply voltage of 3.3 mV. It is apparent that at both operating frequencies, the proposed 10T SRAM design has significantly less read power consumption. This is because only one cell is turned on instead of all the cells in one row in the conventional design. The static and dynamic power also calculated for the two SRAM design with various temperature ranges.
Page(s)	:	166-172
ISSN	:	2319-7323
Source	:	Vol. 4, No.4